Source and drain formation using self-aligned processes

A method of fabricating a semiconductor device, comprising:

• depositing a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate, wherein the gate includes a metal catalyst material for graphene deposition;
• removing an exposed portion of the dielectric layer and removing a first portion of the semiconductor substrate not under the gate, wherein a second portion of the semiconductor substrate remains under the portion of the semiconductor substrate removed;
• depositing a layer of a material on exposed surfaces of the dielectric layer and the semiconductor substrate, wherein the layer of the material creates a source and a drain in a semiconductor device;
• removing the layer of graphene from the gate;
• and
• removing a portion of the layer of the material creating the source and the drain, wherein the portion of the layer of the material creating the source and the drain is removed adjacent to a vertical edge of the portion of the dielectric layer remaining under the gate.