Back to results
US 2019/0164622 A1Published application
Semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorJae Seok KANG
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a test decoding select circuit. The test decoding selective circuit is configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.
Claims19
A semiconductor memory apparatus comprising:
- a test decoding select circuit configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.
Dependencies are inferred from the claim text.