Nonvolatile memory device and method of programming the same

A method of programming a nonvolatile memory device including a plurality of memory cells that are divided into a first cell group, a second cell group and a third cell group according to a level of a threshold voltage, the method comprising:

• applying a programming inhibition voltage to a bit line of each of memory cells of the first cell group;
• applying a programming forcing voltage having a level lower than the programming inhibition voltage to a bit line of each of memory cells of the second cell group;
• performing first programming by applying a first programming pulse to a word line of the plurality of memory cells;
• and
• performing second programming by applying a programming inhibition voltage to bit lines of the memory cells of the first cell group and the second cell group and then applying a second programming pulse to the word line of the plurality of memory cells.

A nonvolatile memory device, comprising:

• a cell array including a plurality of memory cells including first memory cells and second memory cells;
• a row decoder configured to provide a first programming pulse to a word line of the plurality of memory cells in a first programming loop and a second programming pulse to a word line of the plurality of memory cells in a second programming loop;
• a page buffer configured to provide a programming inhibition voltage and a programming forcing voltage having a level lower than a level of the programming inhibition voltage to bit lines of the plurality of memory cells;
• and
• a control logic unit configured to control the row decoder and the page buffer such that the first programming loop and the second programming loop are sequentially performed,
• wherein the programming forcing voltage is applied to a bit line of each of the first memory cells in the first programming loop, and
• the control logic unit is configured to control the page buffer such that the programming inhibition voltage is applied to the bit line of each of the first memory cells in the second programming loop.