Operations on memory cells

An apparatus comprising:

• a controller;
• and
• an array coupled to the controller, wherein the array comprises:
• a first signal line coupled to a first memory cell;
• a second signal line coupled to a second memory cell;
• and
• a third signal line commonly coupled to the first and second memory cells;
• wherein the controller is configured to cause application of a plurality of first signal pulses having a first polarity across the first memory cell during a first time period until the first memory cell is programmed to a desired first state while the second memory cell is inhibited, wherein each first signal pulse causes the first memory cell to move toward the desired first state by causing the first memory cell to snap back;
• and
• wherein the controller is configured to cause application of a plurality of second signal pulses having a second polarity opposite to the first polarity across the second memory cell until the second memory cell is programmed to a desired second state during a second time period while the first memory cell is inhibited, wherein each second signal pulse causes the second memory cell to move toward the desired second state by causing the second memory cell to snap back.

A method, comprising:

• applying a first voltage to first and second signal lines concurrently, wherein the first signal line is coupled to a first memory cell programmed to a first threshold voltage and the second signal line is coupled to a second memory cell programmed to a second threshold voltage greater than the first threshold voltage;
• applying a second voltage to a third signal line while applying the first voltage to first and second signal lines concurrently, wherein the third signal line is commonly coupled to the first and second memory cells, wherein a difference between the first voltage and the second voltage is greater than the first and second threshold voltages such that the first memory cell snaps back at a first time without the second memory cell snapping back at the first time and the second memory cell snaps back at a second time later than the first time;
• determining that the first memory cell is programmed to a first data state in response to detecting that the first memory cell snaps back at the first time responsive to the first voltage being applied to the first signal line and the second signal line concurrently and the second voltage being applied to the third signal line;
• and
• determining that the second memory cell is programmed to the first data state in response to detecting that the second memory cell snaps back at the second time responsive to the first voltage being applied to the second signal line and the second signal line concurrently and the second voltage being applied to the third signal line.

An apparatus, comprising:

• a controller;
• and
• an array coupled to the controller, wherein the array comprises:
• a first signal line coupled to a first memory cell;
• a second signal line coupled to a second memory cell;
• and
• a third signal line commonly coupled to the first and second memory cells;
• wherein the controller is configured to cause application of a first signal to the first signal line and the second signal line concurrently and to cause application of a plurality of signal pulses to the third signal line while the first signal is being applied to the first signal line and to the second signal line concurrently, wherein each signal pulse causes the first and second memory cells to move toward a desired state by causing the first memory cell and the second memory cell to snap back while each signal pulse is being applied;
• wherein the apparatus is configured to turn off current to the first signal line in response to determining each time the first memory cell snaps back and to turn off current to the second signal line in response to determining each time the second memory cell snaps back.