Single-port memory with opportunistic writes
AssigneeWestern Digital Technologies, Inc.
InventorsRan Zamir, David Avraham, Eran Sharon, Idan Alrod
Life of this patent
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Abstract
An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.
Claims20
An apparatus, comprising:
- a first single-port memory;
- a second single-port memory;
- and
- one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory, the one or more control circuits configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and configured to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.
A method, comprising:
- initializing a logical to physical map of a logical address space to a physical memory space according to an initial mapping, the physical memory space includes a first single-port memory and a second single-port memory;
- writing fresh data at locations in the first single-port memory and the second single-port memory according to the initial mapping during an initial period of operation;
- and
- subsequent to the initial period of operation, writing fresh data on a clock cycle to whichever of the first single-port memory or the second single-port memory is not busy with a read command on the clock cycle.
An apparatus, comprising:
- an iterative decoder;
- a first single-port memory coupled to the iterative decoder;
- a second single-port memory coupled to the iterative decoder;
- and
- means for identifying a destination for writing an output of the iterative decoder in the first single-port memory or the second single-port memory in parallel with reading from a physical location in the first single-port memory or the second single-port memory according to a logical to physical map, the destination identified from whichever of the first single-port memory or the second single-port memory does not include the physical location indicated by the logical to physical map.
Dependencies are inferred from the claim text.