Memory system having resistive memory device and operating method thereof

A memory system comprising:

• a memory cell array including a plurality of resistive memory cells that are disposed at intersection points of a plurality of word lines and a plurality of bit lines and are divided into unit blocks including a predetermined number of adjacent memory cells;
• a line counting block suitable for counting an access number of a word line and an access number of a bit line corresponding to an address to output a line counting signal;
• a block counting block suitable for counting an access number of a unit block corresponding to the address to output a block counting signal;
• a data bus inversion (DBI) control block suitable for giving a weighting to each of the line counting signal and the block counting signal and comparing a weighted line counting signal with a weighted block counting signal to generate data bus inversion (DBI) information corresponding to write data;
• and
• a peripheral circuit suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.

An operating method of a memory system, comprising:

• providing a plurality of resistive memory cells that are disposed at intersection points of a plurality of word lines and a plurality of bit lines and are divided into unit blocks including a predetermined number of adjacent memory cells:
• generating data bus inversion (DBI) information corresponding to write data based on an access history of a resistive memory cell corresponding to an address;
• and
• selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.