Synaptic crossbar memory array

An alterable synapse array comprising:

• a plurality of transistors on a device layer;
• a connective layer on said device layer, interlevel vias in said connective layer connecting to selected transistors;
• one or more bottom electrode lines of a first metal on said connective layer, each bottom electrode line connecting to at least one interlevel via;
• one or more amorphous semiconductor synapses, each synapse being on one of said one or more bottom electrode lines;
• and
• an upper electrode layer above said one or more amorphous semiconductor synapses, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, each amorphous semiconductor synapse being between a respective bottom electrode line and an upper electrode line, said second metal being different than the first and one of said first metal and said second metal being a refractory metal.

An Integrated Circuit (IC) chip comprising:

• a plurality of transistors on a device layer;
• a connective layer on said device layer, interlevel vias in said connective layer connecting to selected transistors;
• an alterable synapse array comprising:
• a bottom electrode layer on said connective layer, said bottom electrode layer including one or more bottom electrode lines of a first metal oriented in a first direction, each bottom electrode line connecting to at least one interlevel via,
• one or more amorphous semiconductor ridges, each being on, and coextensive with, one of said one or more bottom electrode lines,
• one or more amorphous semiconductor synapses, each synapse being on one of said one or more bottom electrode lines, and
• an upper electrode layer above said one or more amorphous semiconductor ridges, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, amorphous semiconductor synapses being formed in said ridges between bottom electrode lines and upper electrode lines;
• and
• a plurality of wiring layers connecting said plurality of transistors into IC chip circuits.