Memory device system-on-chip including the same and method of operating the same

A system-on-chip device comprises:

• a memory device configured to store data, the memory device including a memory cell array including a plurality of bit cells;
• a peripheral circuit configured to control the memory cell array;
• a processing circuit configured to provide the data to the memory device before the data is stored in the memory cell array, and receive the data stored in the memory cell array from the memory device;
• and
• a power management integrated circuit (PMIC) configured to provide a first power supply voltage to the memory cell array, and provide a second power supply voltage to the peripheral circuit,
• the peripheral circuit including a voltage generation circuit;
• the voltage generation circuit configured to,
• receive the first power supply voltage and the second power supply voltage,
• adaptively adjust a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and
• apply the word-line driving voltage to a first word-line coupled to first bit cells selected from the plurality of bit cells.

A method of operating a memory device, the memory device including a memory cell array including a plurality of bit cells to store data and a peripheral circuit configured to control the memory cell array, the method comprising:

• generating a result based on a first power supply voltage and a second power supply voltage, the first power supply voltage being supplied to the memory cell array and the second power supply voltage being supplied to the peripheral circuit;
• maintaining a level of a word-line driving voltage applied to a first word-line coupled to first bit cells selected from the plurality of bit cells during a memory operation on the plurality of bit cells, when the result indicates that the first power supply voltage is smaller than or equal to the second power supply voltage;
• and
• decreasing the level of the word-line driving voltage applied to the first word-line coupled to the first bit cells based on a difference between the first power supply voltage and the second power supply voltage during the memory operation on the plurality of bit cells, when the result indicates that the first power supply voltage is greater than the second power supply voltage.