Memory device and operation method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
Life of this patent
Estimating the term…
Abstract
A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
Claims24
An operation method of a memory device which is configured to receive data from an external device through a plurality of data lines, the method comprising:
- generating a first internal code based on a first code and a second code, wherein the first code includes information of a first reference voltage associated with a first data line of the plurality of data lines and the second code includes information about a first decision feedback equalization (DFE) level associated with the first data line;
- generating a second internal code based on a third code and a fourth code, wherein the third code includes information of a second reference voltage associated with a second data line of the plurality of data lines and the fourth code includes information about a second decision feedback equalization (DFE) level associated with the second data line;
- generating a first reference voltage set and a second reference voltage set based on the first internal code and the second internal code, respectively;
- and
- sampling first input data applied on the first data line based on the first reference voltage set and second input data applied on the second data line based on the second reference voltage set.
A memory system comprising:
- a plurality of memory devices, each comprising:
- a memory cell array;
- and
- a data line driver unit configured to drive the memory cell array and receive first input data via a respective first data line and receive second input data via a respective second data line;
- wherein each data line driver unit comprises:
- a first data line driver circuit configured to generate a first reference voltage set based on a first code and a second code associated with the first data line, and to determine bit values of the first input data received through the first data line, based on the first reference voltage set;
- and
- a second data line driver circuit configured to generate a second reference voltage set based on a third and a fourth code associated with the second data line and to determine bit values of the second input data received through the second data line, based on the second reference voltage set.
15-16. (canceled)
The memory system of claim 15, wherein the first reference voltage generator includes:
- an adder circuit that adds the first code and the second code to generate a first sub-code for the first upper reference voltage;
- a first decoder circuit configured to decode the first sub-code;
- an upper reference voltage selector circuit configured to output the first upper reference voltage, based on the decoding result of the first decoder circuit;
- a subtractor circuit that performs a subtraction operation on the first code and the second code to generate a second sub-code for the first lower reference voltage;
- a second decoder circuit configured to decode the second sub-code;
- and
- a lower reference voltage selector circuit configured to output the first lower reference voltage, based on the decoding result of the second decoder.
21-22. (canceled)
A memory device comprising:
- a plurality of memory cells;
- and
- a data line driver circuit configured to:
- generate a first reference voltage set based on a first code and a second code;
- determine bit values of first input data input through a first data line, based on the first reference voltage set;
- generate a second reference voltage set based on a third code and a fourth code;
- and
- determine bit values of second input data input through a second data line, based on the second reference voltage set.
(canceled)
26-29. (canceled)
Dependencies are inferred from the claim text.