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US 2019/0164592 A1Published application
Apparatuses and methods for cache invalidate
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.
Claims21
-20. (canceled)
A system, comprising:
- a bit vector operation capable memory device;
- and
- a host comprising a cache memory system, wherein the host is coupled to the bit vector operation capable memory device and configured to:
- send a bit vector operation request to the bit vector capable memory device for execution;
- and
- execute a received bulk invalidate command corresponding to the bit vector operation request, wherein the bulk invalidate command comprises a base address associated with the bit vector operation request and a length corresponding to a number of cache lines within the cache memory system.
3 more elements
A method for operating a memory device, comprising:
- receiving a processor in memory (PIM) bit vector operation request, wherein the request includes information fields in an instruction packet, the information fields represent various addresses to be used in the bit vector operation;
- and
- causing a bulk invalidate command to be sent to a cache memory system.
A system, comprising:
- a host comprising a cache memory system;
- and
- a bit vector operation capable memory device configured to execute bit vector operation requests provided thereto;
- wherein the host is configured to execute received bulk invalidate commands corresponding to the bit vector operation, and wherein the bulk invalidate command uses a number of cache lines to be invalidated as an argument.
1 more element
Dependencies are inferred from the claim text.