Memory component with efficient write operations
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang
Life of this patent
Estimating the term…
Abstract
A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
Claims20
A memory component comprising:
- a first memory bank comprising a plurality of sub-arrays having sub-rows of memory elements;
- a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array, wherein to perform the write operation, the write driver is to:
- load a burst of write data to the memory bank;
- and
- activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
A method comprising:
- receiving a write command comprising a burst of write data to write to a sub-row of a sub-array of a first memory bank in a first mode;
- loading, by a write driver, the burst of write data to the memory bank;
- and
- activating, by the write driver, a plurality of sense amplifiers for the sub-row to load the burst of write data to the plurality of sense amplifiers
A memory component comprising:
- a first memory bank comprising a plurality of sub-arrays having sub-rows of memory elements, wherein the first memory bank is operable in a first write mode and a second write mode;
- a write driver operatively coupled to a sub-array of the first memory bank, wherein in the first write mode to perform a write operation of an entire sub-row of the sub-array the write driver is to load a burst of write data to a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row;
- and
- a wordline driver operatively coupled to sub-array, wherein in the first write mode the wordline driver is to assert a wordline for the sub-row after the burst of write data is loaded into the plurality of sense amplifiers, wherein asserting the wordline stores the burst of write data from the plurality of sense amplifiers to the plurality of memory elements of the entire sub-row.
Dependencies are inferred from the claim text.