Magnetic random access memory structure and manufacturing method of the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHARRY-HAK-LAY CHUANG, SHENG-CHANG CHEN
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Abstract
The present disclosure provides a magnetic random access memory structure, including an array region, and a logic region adjacent to the array region. The logic region includes a bottom electrode via, a magnetic tunneling junction layer over the bottom electrode via, a top electrode over the MTJ, a conformable oxide layer over the MTJ and the top electrode, and a silicon oxide layer over the conformable oxide layer. The conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.
Claims20
A magnetic random access memory (MRAM) structure, comprising:
- an array region;
- and
- a logic region adjacent to the array region,
- wherein the array region comprises:
- a bottom electrode via (BEVA);
- a magnetic tunneling junction (MTJ) over the BEVA;
- a top electrode over the MTJ;
- a conformable oxide layer over the MTJ and the top electrode;
- and
- a silicon oxide layer over the conformable oxide layer,
- wherein the conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.
A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:
- forming a magnetic tunneling junction (MTJ) structure in an array region;
- forming a protection layer layer over the MTJ structure in the array region and in a logic region adjacent to the array region;
- removing the protection layer in the logic region;
- forming a conformable oxide layer in the array region and the logic region;
- forming a low-k dielectric layer over the conformable oxide layer in the array region and the logic region;
- forming a dielectric stack over the low-k dielectric layer in the array region and the logic region;
- forming an anti-reflective coating (ARC) over the dielectric stack in the array region and the logic region;
- and
- performing an ARC etch back and stopping the etch at the dielectric stack in the array region and the logic region.
A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:
- forming a magnetic tunneling junction (MTJ) structure in an array region;
- forming a first dielectric layer over the MTJ structure in the array region and a logic region adjacent to the array region, the first dielectric layer having a first selectivity;
- forming a first etch stop layer for an anti-reflective coating (ARC) etch back operation, the first etch stop layer having a second selectivity;
- forming a second etch stop layer for a planarization operation over the first etch stop layer, the second etch stop layer having a third selectivity,
- wherein the first selectivity is greater than the second selectivity in the ARC etch back operation, and the first selectivity is greater than the third selectivity in the planarization operation.
Dependencies are inferred from the claim text.