Error detection code hold pattern synchronization
AssigneeMicron Technology, Inc.
InventorStefan Dietrich
Life of this patent
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Abstract
A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.
Claims20
A method, comprising:
- detecting a first scenario, comprising an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both;
- upon detection of the first scenario:
- asserting an error detection code (EDC) hold reset;
- and
- de-asserting the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to a data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
An electronic device, comprising:
- a command clock (CK_t clock);
- a data path clock (WCK_t);
- error detection code (EDC) hold pattern generation circuitry, configured to:
- upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
- assert an EDC hold reset;
- and
- de-assert the EDC hold reset synchronous to a rising edge of the command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
An error detection code (EDC) hold pattern generation circuitry, configured to:
- upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
- assert an EDC hold reset;
- and
- de-assert the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
Dependencies are inferred from the claim text.