Liquid crystal display device and driving method therefor

A driving method of a liquid crystal display device, the liquid crystal display device including

• a plurality of pixels arranged in a matrix pattern having a plurality of rows and a plurality of columns, each of the pixels having a pixel electrode;
• a plurality of gate bus lines, each of the gate bus lines being associated with any of a plurality of pixel rows of the plurality of pixels;
• a plurality of source bus lines, each of the source bus lines being associated with any of a plurality of pixel columns of the plurality of pixels;
• and
• a plurality of TFTs, each of the TFTs being associated with any of the plurality of pixels,
• wherein the plurality of pixel rows include a plurality of pixel row groups, each of the pixel row groups including N pixel rows which adjoin one another in a column direction (N is an integer not less than 2),
• N pixel rows in each of the plurality of pixel row groups are associated with different ones of the source bus lines in each pixel column, and
• where two pixel rows of the plurality of pixel rows which adjoin each other in a column direction and which are included in different ones of the pixel row groups are a first pixel row and a second pixel row, the first pixel row includes a pixel which has one of the pixel electrodes capacitively coupled with one of the gate bus lines which is associated with the second pixel row,
• the method comprising a step of (a) selecting each of the plurality of pixel row groups with a common scan signal voltage in each frame period,
• wherein where, in each frame period, a pth selected one of the pixel row groups is a pth group (p is an integer not less than 1),
• in step (a), when the first pixel row is included in a qth group (q is an integer not less than 1), the second pixel row is included in a (q+1)th group, and
• step (a) includes a step of supplying to the gate bus lines associated with the (q+1)th group a scan signal voltage which switches from low to high before a scan signal voltage supplied to the gate bus lines which are associated with the qth group switches from high to low.