Valuable media handling device with security processor
AssigneeNCR Corporation
InventorsAlexander William Whytock, Philip Keith Staff
Life of this patent
Estimating the term…
Abstract
A valuable media handling device is presented having two security processors. A top box for an escrow module of the valuable media handling device includes a master security processor. The master security processor is connected to a slave security processed located within a safe of the valuable media handling device via an internal bus connection. The master security processor controls and validates operations and modules of the valuable media handling device and the slave security processor controls and validates operations that access the safe for depositing or dispensing valuable media from the safe.
Claims20
A method, comprising:
- controlling and validating, by a first security processor located in a top box outside a safe, modules of and operations being processed on a valuable media handling device;
- and
- communicating, by the first security processor over an internal bus connection, with a second security processor located in the safe when a transaction operation being processed on the valuable media handling device requests access to the safe for depositing valuable media into or dispensing the valuable media from the safe.
A method, comprising:
- receiving, by a master security processor, a command to dispense or deposit valuable media from a valuable media handling device;
- validating, by the master security processor, the command;
- and
- sending, by the master security processor over an internal bus connection, an instruction to a slave security processor located in a safe of the media handling device to dispense from or deposit into the valuable media when the command is validated.
A valuable media handling device, comprising:
- a first security processor is located and secured in a top box;
- a second security processor located in a safe;
- wherein the first security processor is connected to the second security processor through an internal bus connection, wherein the first security processor includes a tamper responsive circuit configured to provide an indication when mesh is broken for a Printed Circuit Board (PCB) of the first security processor, and the first security processor is configured to erase cryptographic keys housed in memory and storage when the indication is received from the tamper responsive circuit.
Dependencies are inferred from the claim text.