Neural network circuits having non-volatile synapse arrays

A synapse circuit comprising:

• a first input signal line for providing a first input signal;
• a second input signal line for providing a second input signal;
• a reference signal line for providing a reference signal;
• first and second output lines for carrying first and second output signals therethrough;
• a cross-coupled latch circuit for storing an electrical signal, including:
• first and second inverters that each have input and output terminals, the input terminal of the first inverter being connected to the output terminal of the second inverter at a first signal node, the input terminal of the second inverter being connected to the output terminal of the first inverter at a second signal node;
• and
• first and second cells for generating the first and second output signals, respectively, each of the first and the second cells including:
• a first upper select transistor having a gate that is electrically coupled to the first input signal line;
• a second upper select transistor having a gate that is electrically coupled to the second input signal line;
• and
• a source of the first upper select transistor and a source of the second upper select transistor being directly connected to a common node,
• the common node of the first cell is electrically coupled to the first signal node of the cross-coupled latch circuit, and the common node of the second cell is electrically coupled to the second signal node of the cross-coupled latch circuit,
• wherein:
• a drain of the first upper select transistor of the first cell is electrically coupled to the first output line and a drain of the first upper select transistor of the second cell is electrically coupled to the second output line,
• a drain of the second upper select transistor of the first cell is electrically coupled to the second output line and a drain of the second upper select transistor of the second cell is electrically coupled to the first output line, and
• the first and second inverters of the cross-coupled latch circuit are electrically coupled to the reference signal line.

A neural network chip, comprising:

• a central processing unit for controlling elements on the neural network chip;
• a sensor for providing input signals;
• a memory unit for storing data;
• a non-volatile neural network unit;
• wherein the central processing unit, the sensor, the memory unit, and the non-volatile neural network unit are electrically coupled, and the non-volatile neural network unit, further comprising:
• a synapse array including a plurality of non-volatile synapses, each of the non-volatile synapses including:
• a first input signal line for providing a first input signal;
• a reference signal line for providing a reference signal;
• a first output line for carrying output signals therethrough;
• and
• a cell for generating the output signal, the cell including:
• a first upper select transistor having a gate that is electrically coupled to the first input signal line;
• and
• a first resistive changing element having one end connected to the first upper select transistor in series and an other end electrically coupled to the reference signal line, a value of the first resistive changing element being programmable to change a magnitude of an output signal,
• wherein a drain of the first upper select transistor of the cell is electrically coupled to the first output line.

A neural network system-on-chip comprising:

• a central processing unit;
• a sensor unit;
• a neural network engine;
• a logic friendly non-volatile memory unit;
• wherein the central processing unit, the sensor unit, the logic friendly non-volatile memory unit, and the neural network engine are coupled by a system bus, and
• the neural network engine can execute without transmitting the data stored in the logic friendly non-volatile memory outside the chip.

A neural network chip, comprising:

• a central processing unit for controlling elements on the chip;
• a non-volatile neural network unit;
• a sensor for providing input signals to the non-volatile neural network;
• a memory unit;
• wherein the central processing unit, the sensor, the memory unit, and the non-volatile neural network unit are electrically coupled, and the non-volatile neural network unit adaptively controls the operating parameters such as voltage and frequency of the central processing unit, the memory unit, and the sensor.