Low-power hardware acceleration method and system for convolution neural network computation

A digital circuit for accelerating computations in a convolutional neural network, comprising:

• an external memory that stores an input vector, a weight vector, and an output vector;
• and
• a control unit, wherein the control unit comprises:
• an on-chip memory that stores log-domain values of the input vector and weight matrix to be processed;
• a pairs selection unit that selects different subsets of pairs of log-domain input vector values and corresponding unprocessed log-domain weight vector values from the on-chip memory, and stores the pair values in a plurality of pairs of registers:
• and
• a core unit that includes a plurality of sub-units wherein each sub-unit performs a multiply-and-aceimiulate operation on the pair values in one pair of registers wherein multiplying the pairs of values comprises adding corresponding pairs of integers in a log domain;
• wherein the core unit simultaneously calculates partial sums of z output values, wherein z is less than a total number of values of the output vector, wherein each partial sum includes a subset of linear domain multiplication results, and the control unit accumulates the partial sums into z corresponding registers associated with z output values.