Vertically Integrated Neuro-Processor

A vertically integrated neuro-processor, comprising:

• a plurality of neural storage-processing units (NSPU's), each of said NSPU's comprising at least a neuro-storage circuit and a neuro-processing circuit, wherein said neuro-storage circuit comprises at least a memory array for storing at least a portion of a synaptic weight, and said neuro-processing circuit performs neural processing with said synaptic weight;
• a memory level and a logic level, wherein said memory array is disposed on said memory level, said neuro-processing circuit is disposed on said logic level, said memory level and said logic level are vertically stacked and communicatively coupled by a plurality of inter-level connections.