Placement and timing aware wire tagging

A system for optimizing design data for a semiconductor circuit, said design data describing a signal line and physical characteristics of said signal line, said system comprising:

• a receiving unit adapted for receiving said design data for said signal line originating at a source and ending at a sink, wherein said receiving unit is also adapted for receiving constraint data describing a blockage area that must be free of buffers present along said signal line from said source to said sink;
• a determination module adapted for determining a segment and a related length of said signal line that would overlap with said blockage area assuming a direct path from said source to said sink, wherein said determination module is also adapted for determining for said segment, based on said length of said segment, whether said segment is route-able without inserting a buffer in said segment while meeting said timing constraints;
• and
• a modifying module adapted for modifying, in case a segment is not route-able without inserting a buffer, said physical characteristics of said signal,
• wherein said determination module and said modifying module are adapted for performing said determination of said segment, said determination, whether said segment length is route-able, and said modification of said physical characteristics of said signal line is performed before placing buffers in said signal line and routing said signal line.

A computer program product for processing design data for a semiconductor circuit, said design data describing a signal line and physical characteristics of said signal line, said computer program product comprising a computer readable storage medium having program instructions embodied therewith, said program instructions being executable by one or more computing systems to cause said one or more computing systems to:

• receive said design data for said signal line originating at a source and ending at a sink;
• receive constraint data describing a blockage area that must be free of buffers present along said signal line from said source to said sink;
• determine a segment and a related length of said signal line that would overlap with said blockage area assuming a direct link from said source to said sink;
• determine for said segment, based on said length of said segment, whether said segment is route-able without inserting a buffer in said segment;
• and
• modify, in case a segment is not route-able without inserting a buffer, data describing said physical characteristics of said signal line,
• wherein said determination of said segment, said determination of whether said segment length is route-able, and said modification of said physical characteristics of said signal line is performed before placing buffers in said signal line and routing said signal line.