Design aware variable fill pattern generator

A method of forming an integrated circuit, comprising:

• providing a mask including mask elements, the mask elements including first mask elements corresponding to functional structures of a physical layer of the integrated circuit, and second mask elements corresponding to fill structures of the physical layer, each second mask element being unconnected to neighboring mask elements, the second mask elements including:
• a first subset of mask elements corresponding to first fill structures having a first size, located in a first region having a first region area and a first fill density, the first fill density defined by a ratio of a first fill area divided by the first region area, the first fill area being an area occupied by the first fill structures in the first region;
• and
• a second subset of mask elements corresponding to second fill structures having a second size, located in a second region different from the first region, the second region having a second region area and a second fill density, the second fill density defined by a ratio of a second fill area divided by the second region area, the second fill area being an area occupied by the second fill structures in the second region,
• wherein the first size is different from the second size, or the first fill density is different from the second fill density;
• and
• patterning the physical layer of the integrated circuit using the mask.