Enabling automatic staging for nets or net groups with vhdl attributes

A computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code being executable by a processor to perform a method comprising:

• inputting the formal specification;
• identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification;
• inputting physical design constraints;
• and
• calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

A system for processing a formal specification of a digital circuit, the specification comprising information about a signal path for forwarding a digital signal from a source to a sink, the system comprising:

• a memory;
• and
• a processor communicatively coupled to the memory, wherein the system performs a method comprising:
• inputting the formal specification;
• identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification;
• inputting physical design constraints;
• and
• calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.