Semiconductor device and failure detection method of the semiconductor device
AssigneeRenesas Electronics Corporation
InventorsKyohei YAMAGUCHI, Daisuke KAWAKAMI, Hiroyuki HAMASAKI
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AssigneeRenesas Electronics Corporation
InventorsKyohei YAMAGUCHI, Daisuke KAWAKAMI, Hiroyuki HAMASAKI
Estimating the term…
A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.
A semiconductor device comprising:
A failure detection method of a semiconductor device that includes a first processor that performs a predetermined interrupt in response to an interrupt request, a plurality of circuit blocks, each outputting an interrupt signal, a first interrupt control circuit that receives the interrupt signals from the circuit blocks and outputs the interrupt request to the first processor and at least one interrupt monitoring circuit that corresponds to at least one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods, the monitoring type indicating a monitoring state of the corresponding interrupt signal, the method comprising:
A failure detection method of a semiconductor device having a first circuit hierarchy and a second circuit hierarchy, the first circuit hierarchy including a plurality of processors that perform a predetermined interrupt in response to an interrupt request, a plurality of circuit blocks, each outputting an interrupt signal, an interrupt control circuit that receives the interrupt signals from the circuit blocks and outputs the interrupt request to one of the processors and at least one interrupt monitoring circuit that corresponds to at least one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods, the monitoring type indicating a monitoring state of the corresponding interrupt signal, the method comprising:
Dependencies are inferred from the claim text.