Semiconductor device and semiconductor system equipped with the same
AssigneeRenesas Electronics Corporation
InventorsKimihiko NAKAZAWA, Takahiro IRITA
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
Claims19
A semiconductor device comprising:
- a master circuit which outputs a first write request signal used for requesting to write data;
- a bus which receives the data and the first write request signal;
- a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal;
- and
- a memory controller which writes the data transmitted from the bus into a storage area of an address which is designated by the first write request signal transmitted from the bus and writes the error detection code transmitted from the bus into a storage area of an address which is designated by the second write request signal transmitted from the bus in storage areas of a memory.
A semiconductor device comprising:
- a master circuit which generates a first read request signal used for requesting to read data written into a memory;
- a bus which receives the first read request signal;
- a bus control unit which is arranged on the bus and generates a second read request signal including second address information corresponding to first address information included in the first read request signal;
- and
- a memory controller which reads the data stored in a storage area of an address designated by the first read request signal which is transmitted from the bus and reads an error detection code for the data which is stored in a storage area of an address designated by the second read request signal which is transmitted from the bus in storage areas of the memory.
Dependencies are inferred from the claim text.