Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

A system comprising:

• a memory to store a first code stored at a first address of a memory and a second code, translated from the first code, at a second address;
• a processor comprising an instruction execution circuit to execute the second code;
• and
• a translation table (TT) controller coupled to a translation table to store a TT entry comprising:
• a mapping between the first address and the second address;
• and
• an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to:
• monitor execution of the second code by the instruction execution circuit;
• and
• update, based on a performance metric of the execution, the attribute value of the TT entry.

A method comprising:

• monitoring, by a translation table (TT) controller associated with a binary translation based (BT) processor, execution of a second code translated from a first code;
• and
• updating, based on a performance metric of the execution, an attribute value of the TT entry, the attribute value comprising at least one of:
• a TT hit count attribute value representing a number of times that the mapping has been used to translate the first code to the second code;
• a loop attribute value indicating whether there are instruction loops in the first code;
• a dynamic execution count attribute value representing a number of instructions in the first code divided by a number of conditional branches in the first code;
• a gear level attribute value representing a number of rounds of optimization in translating the first code to the second code;
• or
• a prefetch attribute value indicating whether the entry is prefetched from a full list of mappings stored in the memory.