Page translation prefetch mechanism
AssigneeIntel Corporation
InventorsNiranjan Cooray, Nicolas Kacevas, David Standring
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Abstract
An apparatus to facilitate page translation prefetching is disclosed. The apparatus includes a translation lookaside buffer (TLB), including a first table to store page table entries (PTEs) and a second table to store tags corresponding to each of the PTEs; and prefetch logic to detect a miss of a first requested address in the TLB during a page translation, retrieve a plurality of physical addresses from memory in response to the TLB miss and store the plurality of physical addresses as a plurality of PTEs in a first TLB entry.
Claims24
An apparatus to facilitate prefetching page translations, comprising:
- a translation lookaside buffer (TLB), including:
- a first table to store page table entries (PTEs);
- and
- a second table to store tags corresponding to each of the PTEs;
- and
- prefetch logic to detect a miss of a first requested address in the TLB during a page translation, retrieve a plurality of physical addresses from memory in response to the TLB miss and store the plurality of physical addresses as a plurality of PTEs in a first TLB entry.
A method to facilitate prefetching page translations, comprising:
- detecting a miss of a first requested address in a translation lookaside buffer (TLB) during a page translation;
- retrieving a plurality of physical addresses from memory in response to the TLB miss;
- and
- storing the plurality of physical addresses as a plurality of PTEs in a first TLB entry.
A system to facilitate prefetching page translations, comprising:
- a memory;
- and
- a memory management unit (MMU) coupled to the memory, including:
- a translation lookaside buffer (TLB), including:
- a first table to store page table entries (PTEs);
- and
- a second table to store tags corresponding to each of the PTEs;
- and
- prefetch logic to detect a miss of a first requested address in the TLB during a page translation, retrieve a plurality of physical addresses from the memory in response to the TLB miss and store the plurality of physical addresses as a plurality of PTEs in a first TLB entry.
Dependencies are inferred from the claim text.