Bandwidth efficient techniques for enabling tagged memories

A computer program product for bandwidth efficient techniques for enabling tagged memories, the computer program product comprising:

• a computer readable storage medium having stored thereon program instructions executable by a processor to cause the processor to:
• receive a cacheline of data;
• hash the cacheline into a plurality of chunks, wherein each chunk includes a pattern of bits;
• store the plurality of chunks in a pattern table, wherein the plurality of chunks are indexed in the pattern table based on the pattern of bits of each chunk;
• identify a repeated pattern of bits of the plurality of chunks and selecting the repeated pattern of bits as candidate pattern, wherein the candidate pattern includes non-zero patterns;
• compare a threshold number of bits of the candidate pattern to the pattern of bits of the plurality of chunks in the pattern table;
• based on the comparison, insert valid bits and a tag into the pattern table for the candidate pattern by replacing bits in the candidate pattern;
• write the candidate pattern, including the valid bits and the tag, into a location of memory corresponding to the candidate pattern;
• wherein comparing the threshold number of bits include matching first 8 bits of the candidate pattern to first 8 bits of entries in the pattern table;
• and
• responsive to the matching, replacing 3 bits after the first 8 bits of the candidate pattern in the pattern table with a valid indicator, and 1 bit after the valid indicator with a 1-bit tag.

A system for bandwidth efficient techniques for enabling tagged memories, the system comprising:

• a memory controller including hashing logic module, counter, and a pattern table;
• a storage medium, the storage medium being coupled to a processor, wherein the storage medium includes a data region and a tag region;
• the processor configured to:
• receive a cacheline of data;
• hash the cacheline into a plurality of chunks, wherein each chunk includes a pattern of bits;
• store the plurality of chunks in a pattern table, wherein the plurality of chunks are indexed in the pattern table based on the pattern of bits of each chunk;
• identify a repeated pattern of bits of the plurality of chunks and selecting the repeated pattern of bits as candidate pattern, wherein the candidate pattern includes non-zero patterns;
• compare a threshold number of bits of the candidate pattern to the pattern of bits of the plurality of chunks in the pattern table;
• based on the comparison, insert valid bits and a tag into the pattern table for the candidate pattern by replacing bits in the candidate pattern;
• write the candidate pattern, including the valid bits and the tag, into a location of the memory corresponding to the candidate pattern;
• wherein comparing the threshold number of bits include matching first 8 bits of the candidate pattern to first 8 bits of entries in the pattern table;
• and
• responsive to the matching, replacing 3 bits after the first 8 bits of the candidate pattern in the pattern table with a valid indicator, and 1 bit after the valid indicator with a 1-bit tag.