Caching bypass mechanism for a multi-level memory

A computing system, comprising:

• a plurality of processing cores;
• a peripheral control hub having an interface to couple to a solid state drive;
• a multi-level memory comprising a higher memory level to act as a memory side cache for one or more lower memory levels;
• memory controller logic circuitry to interface to the multi-level memory, the memory controller logic circuitry comprising policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.

A method, comprising:

• keeping a history of most recently requested data items that compete for same caching space in a higher level of a multi-level memory, the higher level acting as a memory-side cache for one or more lower levels of the memory;
• identifying certain data items that map to the caching space as not being eligible for keeping in the caching space;
• and,
• preventing the certain data items from being kept in the caching space as part of processing accesses for the certain data items.