Accelerator memory coherency with single state machine
AssigneeInternational Business Machines Corporation
InventorsKenneth M. Valk, Guy L. Guthrie, Derek E. Williams, Michael S. Siegel, John D. Irish
Life of this patent
Estimating the term…
Abstract
A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.
Claims20
A computer system for accelerator memory coherency comprising:
- a bus;
- an accelerator coupled with an accelerator memory;
- a state machine in communication with the accelerator memory and the bus, wherein the state machine is configured to:
- master a claw-back request for an address line issued by the accelerator via the bus;
- receive a cast-out push request with a matching address line;
- receive a first combined-response associated with the cast-out push request;
- receive data associated with the modified address line;
- and
- issue a claw-back response to the accelerator with the data associated with the modified address line.
A method for accelerator memory coherency comprising:
- issuing a claw-back request, received from an accelerator, for an address line;
- receiving a cast-out push request with a matching address line;
- receiving a first combined-response associated with the cast-out push request;
- receiving data associated with the modified copy of the address line;
- and
- issuing a claw-back response, to the accelerator, with the data associated with the modified version of the address line.
A computer program product for accelerator memory coherency, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to perform a method comprising:
- issuing a claw-back request via a bus;
- detecting a cast-out push request from a cache controller associated with a cache having a modified address line;
- retrieving the push request;
- receiving a cache combined response, from the cache controller, associated with the cast-out push request;
- receiving a master-combined response associated with the claw-back request;
- receiving, from the cache controller, data associated with the modified address line;
- and
- issuing a claw-back response with the data associated with the modified address line.
Dependencies are inferred from the claim text.