Efficient cache memory having an expiration timer
AssigneeInternational Business Machines Corporation
InventorEiji Tosaka
Life of this patent
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Abstract
In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.
Claims18
A method, comprising:
- selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer.
A system, comprising:
- a processing circuit having a cache memory therein;
- a ring buffer;
- and
- logic integrated with the processing circuit, executable by the processing circuit, or integrated with and executable by the processing circuit, the logic being configured to cause the processing circuit to:
- selectively invalidate data stored in at least one cache line of the cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than a round-trip time for the processing circuit to process a plurality of blocks of data stored sequentially to the ring buffer.
A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the embodied program instructions being executable by a processing circuit to cause the processing circuit to:
- selectively invalidate, by the processing circuit, data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed,
- wherein the predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer.
Dependencies are inferred from the claim text.