Multi-level system memory with a battery backed up portion of a non volatile memory level
AssigneeIntel Corporation
InventorsZhe WANG, Alaa R. ALAMELDEEN
Life of this patent
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Abstract
An apparatus is described. The apparatus includes memory control logic circuitry having circuity to a limit an amount of dirty data kept in a volatile level of a multi-level memory. The volatile level of the multi-level memory to act as a cache for a non-volatile, lower level of the multi-level memory. The amount of dirty data in the cache to be limited by the memory control logic circuitry to less than the capacity of the cache.
Claims20
An apparatus, comprising:
- memory control logic circuitry comprising circuity to a limit an amount of dirty data kept in a volatile level of a multi-level memory, the volatile level of the multi-level memory to act as a cache for a non-volatile, lower level of the multi-level memory, the amount of dirty data in the cache to be limited by the memory control logic circuitry to less than the capacity of the cache.
A computer system, comprising:
- a plurality of processing cores;
- a multi-level memory comprising a volatile level and a lower, non-volatile level, the volatile level of the multi-level memory to act as a cache for a non-volatile, lower level of the multi-level memory;
- memory control logic circuitry coupled to the multi-level memory, the memory control logic circuitry to limit an amount of dirty data kept in the volatile level of the multi-level memory to less than the capacity of the cache;
- and,
- a solid state drive interface.
The computer system of claim 17 wherein the memory control logic is to write data into the volatile level of the memory according to a write back mode when the amount of dirty data in the volatile level is less than a second preset threshold value that is less than the preset value.
An apparatus, comprising:
- a memory module to implement a multi-level memory, the memory module comprising volatile memory to implement a volatile level of the multi-level memory and non-volatile memory to implement a non-volatile level of the multi-level memory, the volatile memory to act as a cache for the non-volatile memory, the memory module comprising memory control logic circuitry to limit an amount of dirty data kept in the volatile memory to less than the capacity of the volatile memory.
Dependencies are inferred from the claim text.