Novel memory device

A method, comprising:

• reading a first word from a memory array, wherein the first word comprises a plurality of data bits that form N−1 groups and a plurality of parity bits, corresponding to the first word, that form a first group attached to the N−1 groups, and wherein the first group of parity bits and the N−1 groups of data bits are each associated with a group index and N is a positive integer greater than 2;
• receiving a partial-write request to update the data bits of a first one of the N−1 groups;
• providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits, corresponding to the second word, that form a second group by corresponding group indexes of the second one of the N−1 groups and the second group to the group index of the first group of parity bits and the group index of the first one of the N−1 groups, respectively;
• and
• writing a part of the second word to the memory array.

A memory device, comprising:

• a plurality of memory cells that are configured to present a first word,
• wherein the first word comprises a plurality of data bits that form N−1 groups and a plurality of parity bits, corresponding to the first word, that form a first group attached to the N−1 groups, and wherein the first group of parity bits and the N−1 groups of data bits are each associated with a group index and N is a positive integer greater than 2;
• and
• a control logic circuit, coupled to the plurality of memory cells, and configured to:
• in response to a request to update the data bits of a first one of the N−1 groups, provide a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits, corresponding to the second word, that form a second group, wherein the respective group indexes of the first one of the N−1 groups and the second group of updated parity bits are the same;
• and
• update part of the first word using the second word.