Decoding method, memory storage device and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit, coupled to a host system;
• a rewritable non-volatile memory module, comprising a plurality of memory cells;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to transmit a read command sequence instructing the rewritable non-volatile memory module to read at least one of the memory cells by using at least one read voltage level to obtain a codeword,
• wherein the memory control circuit unit is further configured to perform a parity check operation on the codeword to generate a syndrome sum corresponding to the codeword,
• wherein the memory control circuit unit is further configured to dynamically adjust a first parameter used in a first decoding operation based on whether the syndrome sum is less than a first predetermined value and perform the first decoding operation on the codeword by using the first parameter,
• wherein the adjusted first parameter affects a probability that a first bit in the codeword is considered as an error bit in the first decoding operation.

A memory control circuit unit, for controlling a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory control circuit unit comprises:

• a host interface, coupled to a host system;
• a memory interface, coupled to the rewritable non-volatile memory module;
• an error checking and correcting circuit;
• and
• a memory management circuit, coupled to the host interface, the memory interface, and the error checking and correcting circuit,
• wherein the memory management circuit is configured to transmit a read command sequence instructing the rewritable non-volatile memory module to read at least one of the memory cells by using at least one read voltage level to obtain a codeword,
• wherein the error checking and correcting circuit is configured to perform a parity check operation on the codeword to generate a syndrome sum corresponding to the codeword,
• wherein the error checking and correcting circuit is further configured to dynamically adjust a first parameter used in a first decoding operation based on whether the syndrome sum is less than a first predetermined value, and perform the first decoding operation on the codeword by using the first parameter,
• wherein the adjusted first parameter affects a probability that a first bit in the codeword is considered as an error bit in the first decoding operation.