High efficiency redundant array of independent memory
AssigneeInternational Business Machines Corporation
InventorsPatrick J. MEANEY, Christian JACOBI, Barry M. TRAGER
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Abstract
A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.
Claims20
A memory system comprising:
- a plurality of memory modules, wherein each memory module of the plurality of memory modules has a predefined number of sets of memory devices including one or more data memory devices for data and one or more error correction code (ECC) memory devices for ECC, wherein the ECC memory devices carry a predetermined number of ECC symbols in order to facilitate redundant array of independent memory (RAIM) functionalities for the plurality of memory modules;
- a host comprising a memory controller executing RAIM operations, based on the ECC symbols from the memory modules;
- and
- a predefined number of channels coupling the host and the plurality of memory modules, wherein each channel of the predefined number of channels corresponds to a set of the predefined number of sets, wherein the predefined number of sets communicate with the host via respectively corresponding channels of the predefined number of channels.
A memory system comprising:
- a plurality of memory modules, wherein each memory module of the plurality of memory modules has a predefined number of sets of memory devices including one or more data memory devices for data, one or more error correction code (ECC) memory devices for ECC, and one or more buffer, wherein the ECC memory devices carry a number of ECC symbols in order to facilitate redundant array of independent memory (RAIM) functionalities for the plurality of memory modules;
- a host comprising a memory controller executing RAIM operations, based on the ECC symbols from the memory modules;
- and
- a predefined number of channels coupling the host and the plurality of memory modules for memory operations, wherein the predefined number of channels is equal to the predefined number of the sets of the memory devices, and wherein each of the memory module has the same number of set of the memory devices as the rest of the memory modules.
A method for controlling a memory system comprising:
- obtaining, by a host, a predetermined number of Error Correction Code (ECC) symbols from each memory operation in a predefined number of homogeneous memory modules;
- decoding the ECC symbols for supported Redundant Array of Independent Memory (RAIM) functionalities;
- and
- executing RAIM operation as specified in an ECC scheme of the memory system, wherein at least one of the RAIM functionalities is selected from the group consisting of:
- memory error detection, memory error correction, chip marking, channel marking, chipkill, per-rank channel marking, graduated chip marking, hierarchical channel marking, static and dynamic lane sparing, channel cyclic redundancy check (CRC) checking, channel recovery, dynamic channel marking, power save marking, fourth generation double data rate memory (DDR4) support, fifth generation double data rate memory (DDR5) support, system scrub, initialization, self-test, and OpenCAPI (Coherent Accelerator Processor Interface) memory channel interface.
Dependencies are inferred from the claim text.