Arithmetic logic unit

An arithmetic logic unit comprising:

• a first routing grid coupled to N data lanes, wherein the first routing grid is adapted to drive first data to the N data lanes, wherein N is an integer that is greater than one;
• a second routing grid coupled to the N data lanes, wherein the second routing grid is adapted to drive second data to the N data lanes;
• a pre-processing unit;
• and
• N input buffers;
• wherein each of the N data lanes comprises a reduction unit, a cyclic accumulator buffer coupled to the reduction unit, and N functional units with first inputs from the first routing grid and second inputs from the second routing grid;
• wherein the N functional units of each data lane are operable to compute a first function of the respective first data on the respective first inputs and a second function of the respective second data on the respective second inputs;
• wherein the reduction unit of each data lane is adapted to receive output signals from N functional units of the data lane, wherein the reduction unit is configured to perform a reduction operation and output an output result;
• wherein the first routing grid comprises N inputs that are coupled to N outputs;
• wherein each output out of the N outputs of the first routing grid is coupled to a single data lane;
• wherein the arithmetic logic unit is configured to perform a filtering operation by a single dimensional filter that is represented by F coefficients, wherein F is a positive integer that is greater than N;
• and
• wherein S is a smallest integer for which a ratio between F and S does not exceed N;
• wherein, for each value s that ranges between 0 and (S-1), the arithmetic logic unit is configured to perform a part of the filtering operation by:
• (i) receiving, by the pre-processing unit, N*2 pixels starting from a (X+s)'th pixel;
• (ii) generating, as the first data, N slices that differ from each other by one pixel, wherein different slices of the N slices are fed, by the first routing grid, to different data lanes of the N data lanes;
• (iii) feeding, by the second routing grid, as the second data, and to each of the N data lanes a coefficient vector that starts from the s'th coefficient of the single dimensional filter, wherein each data lane is configured to perform a multiplication between a slice provided to the data lane and the coefficient vector, and wherein each reduction unit is configured to calculate a sum by adding N products calculated by the N functional units of the data lane.