Priority instruction handling with optimized issue queue design
AssigneeInternational Business Machines Corporation
InventorsSatish Kumar Sadasivam, Puneeth A. H. Bhat, Shruti Saxena
Life of this patent
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Abstract
Microprocessor with multiple issue queues in a microprocessor, where at least one of the issue queues is an adjustable mode queue that can be set to act as either of a priority queue, or a regular queue, with respect to intake of new instructions and/or outflow of old instructions. A set of summary bit value(s) can be set to control whether the adjustable mode queue has instruction intake priority and/or instruction outflow priority relative to the other issue queue(s).
Claims15
A processor comprising:
- an instruction intake module;
- a plurality of issue queue register sets including a first adjustable mode queue register set and a first regular queue register set;
- an instruction execution module;
- and
- control logic;
- wherein:
- each issue queue register set of the plurality of issue queue register sets is structured, connected and/or programmed to temporarily store instructions as instructions are passed from the instruction intake module to the instruction execution module, with the instructions each being characterized by a priority value;
- and
- the control logic is structured and/or programmed to selectively choose between at least the following two modes of operation:
- (i) a first mode where the first adjustable queue register set operates at a higher intake and outflow priority than the first regular queue register set, and (ii) a second mode where the first adjustable queue register set operates at equal intake and outflow priority to the first regular queue register set.
4-6. (canceled)
(canceled)
10-12. (canceled)
A processor comprising:
- an instruction intake module;
- a plurality of issue queue register sets including a first adjustable mode queue register set and a first regular queue register set;
- an instruction execution module;
- and
- control logic;
- wherein:
- each issue queue register set of the plurality of issue queue register sets is structured, connected and/or programmed to temporarily store instructions as instructions are passed from the instruction intake module to the instruction execution module, with the instructions each being characterized by a priority value;
- and
- the control logic is structured and/or programmed to selectively choose between at least the following two modes of operation:
- (i) a first mode where the first adjustable queue register set operates at a higher intake priority than the first regular queue register set, and (ii) a second mode where the first adjustable queue register set operates at equal intake priority to the first regular queue register set.
(canceled)
A processor comprising:
- an instruction intake module;
- a plurality of issue queue register sets including a first adjustable mode queue register set and a first regular queue register set;
- an instruction execution module;
- and
- control logic;
- wherein:
- each issue queue register set of the plurality of issue queue register sets is structured, connected and/or programmed to temporarily store instructions as instructions are passed from the instruction intake module to the instruction execution module, with the instructions each being characterized by a priority value;
- and
- the control logic is structured and/or programmed to selectively choose between at least the following two modes of operation:
- (i) a first mode where the first adjustable queue register set operates at a higher outflow priority than the first regular queue register set, and (ii) a second mode where the first adjustable queue register set operates at equal outflow priority to the first regular queue register set.
19-20. (canceled)
Dependencies are inferred from the claim text.