Buffered instruction dispatching to an issue queue

A system comprising:

• a dispatching unit of a processor;
• an issue queue buffer of the processor;
• a first issue queue partition of the processor;
• a second issue queue partition of the processor;
• and
• a controller of the processor to perform a plurality of operations comprising:
• dispatching from the dispatch unit a first group of instructions selected from a first plurality of instructions to the first issue queue partition in a first cycle;
• passing a second group of instructions selected from the first plurality of instructions to the issue queue buffer of the processor in the first cycle;
• passing the second group of instructions from the issue queue buffer to the first issue queue partition in a second cycle;
• and
• dispatching a third group of instructions selected from a second plurality of instructions to the second issue queue partition in the second cycle.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

• dispatching from a dispatch unit of the processor a first group of instructions selected from a first plurality of instructions to a first issue queue partition of the processor in a first cycle;
• passing a second group of instructions selected from the first plurality of instructions to an issue queue buffer of the processor in the first cycle;
• passing the second group of instructions from the issue queue buffer to the first issue queue partition in a second cycle;
• and
• dispatching a third group of instructions selected from a second plurality of instructions to a second issue queue partition in the second cycle.