Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor

A system comprising:

• a dependency matrix in an issue queue of an out-of-order processor;
• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• tracking dependencies between instructions in an issue queue, wherein the tracking comprises, for each instruction in the issue queue:
• tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction;
• tracking as a single group, a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions;
• tracking for each source register used by the instruction, an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution;
• and
• based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution:
• indicating that the instruction is ready for issuance based at least in part on the instruction not having a source register with contents that are dependent on results from the removed instruction;
• and
• waiting for a notification that the removed instruction has finished execution before indicating that the instruction is ready for issuance based at least in part on the instruction having a source register with contents that are dependent on results from the removed instruction.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

• tracking dependencies between instructions in an issue queue, wherein the tracking comprises, for each instruction in the issue queue:
• tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction;
• tracking as a single group, a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions;
• tracking for each source register used by the instruction, an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution;
• and
• based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution:
• indicating that the instruction is ready for issuance based at least in part on the instruction not having a source register with contents that are dependent on results from the removed instruction;
• and
• waiting for a notification that the removed instruction has finished execution before indicating that the instruction is ready for issuance based at least in part on the instruction having a source register with contents that are dependent on results from the removed instruction.