Parallel decimal multiplication hardware with a 3x generator

A parallel decimal multiplication hardware architecture comprising:

• a 3× generator;
• at least one additional generator;
• a multiplier recoder;
• a partial product tree;
• and
• a decimal adder,
• the parallel decimal multiplication hardware architecture configured to produce a final product from a multiplicand and a multiplier by:
• generating, by the 3× generator, the at least one additional generator, and the multiplier recoder of the parallel decimal multiplication hardware architecture, decimal partial products from the multiplicand and the multiplier;
• executing, by the partial product tree of the parallel decimal multiplication hardware architecture, a reduction of the decimal partial products to produce two corresponding partial product accumulations;
• and
• adding, by the decimal adder of the parallel decimal multiplication hardware architecture, the two corresponding partial product accumulations of the decimal partial products to produce the final product.

A system comprising:

• a 3× generator;
• at least one additional generator;
• a multiplier recoder;
• a partial product tree;
• and
• a decimal adder,
• the system configured to produce a final product from a multiplicand and a multiplier by:
• generating, by the 3× generator, the at least one additional generator, and the multiplier recoder, decimal partial products from the multiplicand and the multiplier;
• executing, by the partial product tree, a reduction of the decimal partial products to produce two corresponding partial product accumulations;
• and
• adding, by the decimal adder, the two corresponding partial product accumulations of the decimal partial products to produce the final product.