Buffer size optimization in a hierarchical structure

An integrated circuit comprising:

• a field programmable gate array, the field programmable gate array comprising:
• a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records, the compare unit comprising a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record;
• and
• another compare unit on another level of the plurality of levels of the hierarchical structure, the other compare unit comprising another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record, wherein a size of the one or more other buffers of the other buffer pair is insufficient to store the record;
• and
• wherein the one compare unit and the other compare unit are adapted to sort a plurality of records.

A method comprising:

• providing a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records, the compare unit comprising a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record;
• providing another compare unit on another level of the plurality of levels of the hierarchical structure, the other compare unit comprising another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record, wherein a size of the one or more other buffers of the other buffer pair is insufficient to store the record;
• and
• wherein the one compare unit and the other compare unit are adapted to sort a plurality of records.