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US 2019/0163401 A1Published application
Semiconductor memory device and reset method thereof
AssigneeWinbond Electronics Corp.
InventorKazuki Yamauchi
Life of this patent
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AssigneeWinbond Electronics Corp.
InventorKazuki Yamauchi
Estimating the term…
The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device (100) of the disclosure includes a master side memory chip (200) and at least one slave side memory chip (300). A controller (230) of the master side memory chip (200) selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller (230) controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.
A semiconductor memory device comprising a master side memory chip and at least one slave side memory chip, wherein the master side memory chip and the slave side memory chip are electrically connected, wherein,
A reset method of a semiconductor memory device, wherein the semiconductor memory device comprises a master side memory chip and at least one slave side memory chip, wherein the master side memory chip and the slave side memory chip are electrically connected, wherein,
A reset method of a semiconductor memory device, wherein the semiconductor memory device comprises a master side memory chip and at least one slave side memory chip, wherein the master side memory chip and the slave side memory chip are electrically connected, wherein,
Dependencies are inferred from the claim text.