Semiconductor memory
AssigneeToshiba Memory Corporation
InventorNaoya TOKIWA
Life of this patent
Estimating the term…
Abstract
A semiconductor memory includes a first plane that includes a first memory cell array, a second plane that includes a second memory cell array, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority. When a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.
Claims20
A semiconductor memory comprising:
- a first plane that includes a first memory cell array;
- a second plane that includes a second memory cell array;
- and
- a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority,
- wherein when a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.
A memory system comprising:
- a controller;
- and
- a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane in response to a first command from the controller and a second circuit configured to store a second priority for a second operation performed on the second plane in response to a second command from the controller, wherein
- the controller is configured to control the first and second operations based on the first priority and the second priority, such that when a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.
A method of performing parallel operations in a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, said method comprising:
- controlling the first and second operations based on the first priority and the second priority, such that when a value of the second priority is higher than a value of the first priority, adjusting a timing of a process executed in the first operation so as to not overlap with a timing of a process executed in the second operation.
Dependencies are inferred from the claim text.