Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus
AssigneeIntel Corporation
InventorsChristopher E. COX, Christopher P. MOZAK
Life of this patent
Estimating the term…
Abstract
An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
Claims20
An apparatus, comprising:
- a memory controller having an interface to communicate with a memory the memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface, the memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
A computing system, comprising:
- a network interface;
- a plurality of processing cores;
- a memory;
- a memory controller having an interface to communicate with a memory, the memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface, the memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
A memory, comprising:
- an interface to communicate with a memory controller, the memory comprising logic circuitry to comprehend one of multiple possible write values to be written to the memory during a write operation with multiple bits of a command that is sent on a command address bus that flows into the interface, the memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
Dependencies are inferred from the claim text.