Mechanism for enabling full data bus utilization without increasing data granularity

A dynamic random access memory (DRAM) device comprising:

• first and second memory portions, wherein each of the first and second memory portions includes a plurality of memory banks;
• and
• an interface to receive memory access requests from a memory controller, including row commands and, for each row command, an indication of which of the first and second memory portions is to be accessed, an indication of which memory bank of the corresponding plurality is to be accessed, and column selection information, wherein the interface is configured to receive consecutive row commands such that a time between receipt of consecutive row commands directed to memory banks within different ones of the first and second memory portions, is shorter than a time between receipt of consecutive row commands directed to memory banks within a same one of the first and second memory portions;
• wherein the interface is further configured to exchange data with the memory controller via a common signaling line in association with each of the memory access requests, irrespective of which of the first and second memory portions is to be accessed, irrespective of which of memory bank k to be accessed, and irrespective of which column of a memory bank is selected.

A dynamic random access memory (DRAM) device comprising:

• an interface to couple the DRAM device to a memory controller, via a control path, to receive memory access requests from the memory controller, and via a data path, to exchange data with the memory controller in association with each of the memory access requests;
• first and second memory portions, wherein each of the first and second memory portions includes a plurality of memory banks;
• and
• wherein the memory access requests include row commands, including for each row command, an indication of which of the first and second memory portions is to be accessed and an indication of which memory bank of the corresponding plurality is to be accessed;
• wherein the interface is configured to couple the row commands to access control circuitry respective to the first and second portions, in accordance with the indication accompanying each given one of the row commands;
• and
• wherein the interface is configured to receive consecutive row commands such that a time between receipt of consecutive row commands directed to memory banks within different ones of the first and second memory portions, is shorter than a time between receipt of consecutive row commands directed to memory banks within a same one of the first and second memory portions.