Data accessing method, memory controlling circuit unit and memory storage device
AssigneePhison Electronics Corp.
InventorsWei Lin, An-Cheng Liu, Lih Yuarn Ou, Szu-Wei Chen
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Abstract
A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.
Claims30
A data accessing method for a rewritable non-volatile memory module, the rewritable non-volatile memory module having a plurality of physical erasing units, each physical erasing unit among the physical erasing units having a plurality of physical programming units, the data accessing method comprising:
- reading a first physical programming unit among the physical programming units to obtain first data by using at least one first read voltage among a plurality of read voltages;
- reading the first physical programming unit to obtain second data by using at least one second read voltage among the read voltages;
- inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine;
- determining a third read voltage for reading the first physical programming unit among the read voltages by the numerical calculation engine according to the first state parameter and the second state parameter;
- and
- reading the first physical programming unit to obtain third data by using the third read voltage.
A memory controlling circuit unit for controlling a rewritable non-volatile memory module, the rewritable non-volatile memory module having a plurality of physical erasing units, each physical erasing unit among the physical erasing units having a plurality of physical programming units, the memory controlling circuit unit comprising:
- a host interface, configured to couple to a host system;
- a memory interface, configured to couple to a rewritable non-volatile memory module;
- a numerical calculation engine;
- and
- a memory management circuit, coupled to the host interface, the memory interface and the numerical calculation engine,
- wherein the memory management circuit is configured to read a first physical programming unit among the physical programming units to obtain first data by using at least one first read voltage among a plurality of read voltages,
- wherein the memory management circuit is further configured to read the first physical programming unit to obtain second data by using at least one second read voltage among the read voltages,
- wherein the memory management circuit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into the numerical calculation engine, and
- the numerical calculation engine is configured to determine a third read voltage for reading the first physical programming unit among the read voltages according to the first state parameter and the second state parameter,
- wherein the memory management circuit is further configured to read the first physical programming unit to obtain third data by using the third read voltage.
A memory storage device, comprising:
- a connection interface unit, configured to couple to a host system;
- a rewritable non-volatile memory module having a plurality of physical erasing units, each physical erasing unit among the physical erasing units having a plurality of physical programming units;
- and
- a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, and having a numerical calculation engine,
- wherein the memory controlling circuit unit is configured to read a first physical programming unit among the physical programming units to obtain first data by using at least one first read voltage among a plurality of read voltages,
- wherein the memory controlling circuit unit is further configured to read the first physical programming unit to obtain second data by using at least one second read voltage among the read voltages,
- wherein the memory controlling circuit unit is further configured to input a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into the numerical calculation engine, and determine a third read voltage for reading the first physical programming unit among the read voltages by the numerical calculation engine according to the first state parameter and the second state parameter,
- wherein the memory controlling circuit unit is further configured to read the first physical programming unit to obtain third data by using the third read voltage.
Dependencies are inferred from the claim text.