Apparatus for Power Consumption Reduction in Electronic Circuitry and Associated Methods

An apparatus comprising:

• a first storage circuit to store information, the first storage circuit having a normal mode of operation, and a low-power mode of operation in which the first storage circuit consumes less power than in the normal mode of operation;
• a second storage circuit to retain a state of the first storage circuit in the low-power mode of operation, the retained state to be provided to the first storage circuit when the first storage circuit resumes the normal mode of operation;
• and
• a power-supply circuit to provide a normal supply voltage to the first storage circuit in the normal mode of operation, the power-supply circuit comprising a first non-linear circuit to provide a compressed supply voltage to the second storage circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

A method comprising:

• storing information by using a first storage circuit, the first storage circuit having a normal mode of operation, and a low-power mode of operation in which the first storage circuit consumes less power than in the normal mode of operation;
• retaining, by using a second storage circuit, a state of the first storage circuit in the low-power mode of operation, the retained state to be provided to the first storage circuit when the first storage circuit resumes the normal mode of operation;
• and
• supplying, by using a power-supply circuit, a normal supply voltage to the first storage circuit in the normal mode of operation, the power-supply circuit using a first non-linear circuit to provide a compressed supply voltage to the second storage circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.