Core off sleep mode with low exit latency
AssigneeNVIDIA Corporation
InventorsThomas E. DEWEY, Narayan KULSHRESTHA, Ramachandiran V, Sachin IDGUNJI, Lordson YUE
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Abstract
An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.
Claims30
A computer system, comprising:
- a processor configured to execute instructions at least in part in response to user input;
- and
- a graphics processor comprising at least one processing core configured to generate images at least in part in response to the executing instructions and the user input, and at least one data link interface,
- wherein the graphics processor includes a power management circuit configured to repetitively transition, transparently to a user viewing the generated images while said instructions are executing, to and from a low power mode in which the at least one processing core is unpowered while the at least one data link interface remains powered.
A processor comprising one or more processing cores and at least one data link interface, wherein the processor is operable in a low power mode in which the one or more processing cores are unpowered and the at least one data link interface is powered on.
A method comprising:
- detecting an idle processing state in a processor;
- in response to the detecting, entering the processor into a low power mode in which power is off to the at least one processing core on and power is on to the at least one data link interface;
- and
- in response to a wake signal, entering the processor into a full power mode in which power is on to both the at least one core and the at least one data link interface.
A system on a chip (SoC), comprising:
- a central processing unit (CPU);
- at least one data link coupled to the CPU;
- and
- a graphics processing unit (GPU) comprising one or more processing cores and at least one data link interface for communicating over the at least one data link, wherein the GPU is operable in a low power mode in which the one or more processing cores are unpowered and the at least one data link interface is powered on.
Dependencies are inferred from the claim text.