System, Apparatus And Method For In-Field Self Testing In A Diagnostic Sleep State
AssigneeIntel Corporation
InventorsVedvyas Shanbhogue, Jeff Huxel, Wei Li, Sanjoy Mondal, Arvind Raman
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Abstract
In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a first core;
- and
- an interface circuit coupled to the first core to interface the first core to additional circuitry of the processor, wherein in response to an in-field self test instruction, the first core is to save a state of the first core to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state, wherein the first core appears to be inactive in the diagnostic sleep state.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving, in a core of a processor, an instruction to initiate an in-field self test of the core;
- in response to the instruction, saving a state of the core and a state of shared circuitry of the processor to a first memory of the processor;
- obtaining a test pattern from a storage and storing the test pattern in a shared cache memory of the processor;
- programming a test controller of the processor with operating parameters for the in-field self test, based at least in part on configuration information associated with the test pattern;
- and
- entering into a diagnostic sleep state and in response to a signal from the test controller, executing the in-field self test during the diagnostic sleep state.
A system comprising:
- a multicore processor including a shared cache memory, a plurality of cores to execute functional operations, an interface circuit to interface the plurality of cores to another portion of the multicore processor and a power controller coupled to the plurality of cores, wherein a first core of the plurality of cores is to enter into a diagnostic sleep state in which the first core is isolated in response to an instruction to execute an in-field self test while at least the another portion of the multicore processor continues to execute functional operations, the first core to save a state of the first core and a state of the interface circuit to a first storage, obtain a self-test suite and store the self-test suite in the shared cache memory, execute the self-test suite during the diagnostic sleep state and report a result of the execution of the self-test suite to the power controller;
- and
- a system memory to store the self-test suite.
Dependencies are inferred from the claim text.