Power gating control system and control method thereof
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
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Abstract
A power gating control system may be provided. The power gating control system may include a semiconductor apparatus including a logic circuit block which is coupled with a power supply terminal through a power gating transistor. The power gating control system may include a tester configured to control the semiconductor apparatus such that a test for the logic circuit block is performed by using test data while changing a body bias value of the power gating transistor, and update a body bias value satisfying a predetermined test condition, in the semiconductor apparatus.
Claims11
A power gating control system comprising:
- a semiconductor apparatus including a logic circuit block which is coupled with a power supply terminal through a power gating transistor;
- and
- a tester configured to control the semiconductor apparatus such that a test for the logic circuit block is performed by using test data while changing a body bias value of the power gating transistor, and update a body bias value satisfying a predetermined test condition, in the semiconductor apparatus.
A power gating control system comprising:
- a semiconductor apparatus including a plurality of logic circuit blocks which are coupled with a power supply terminal through a plurality of power gating transistors, respectively, and a plurality of switches which are respectively coupled between coupling nodes of the plurality of power gating transistors and the plurality of logic circuit blocks;
- and
- a tester configured to control the semiconductor apparatus such that a test for the plurality of logic circuit blocks is performed by using test data while performing at least one of an on and off (on/off) combination change of the plurality of switches and a body bias change of the plurality of power gating transistors, and update a first body bias value and a first on/off combination satisfying a predetermined test condition, in the semiconductor apparatus.
A power gating control method of a semiconductor apparatus including a plurality of logic circuit blocks which are coupled with a power supply terminal through a plurality of power gating transistors, respectively, and a plurality of switches which are coupled between coupling nodes of the plurality of power gating transistors and the plurality of logic circuit blocks, the power gating control method comprising:
- a body bias optimizing act of determining whether it is a pass or a fail (pass/fail), by performing a test for the plurality of logic circuit blocks while changing a body bias of the plurality of power gating transistors, and setting the body bias of the plurality of power gating transistors, to a body bias value at the time of a final pass.
Dependencies are inferred from the claim text.