Test apparatus for signal integrity testing of connectors

A test apparatus for signal integrity comprising:

• a host compliance printed circuit board having a first circuit plane and a second circuit plane separated by at least one dielectric layer;
• a first row of surface mount pads disposed on the first circuit plane, the first row of surface mount pads including a first pad and a second pad;
• a second row of surface mount pads disposed on the first circuit plane and spaced from the first row of surface mount pads;
• a third row of surface mount pads disposed on the first circuit plane and spaced from the first row of surface mount pads and the second row of surface mount pads;
• and
• a first and second differential pair of circuit lines disposed on the first circuit plane, the first differential circuit line having one end coupled to the first pad, the second differential circuit line having one end coupled to the second pad, the first and second differential pair of circuit lines extending from the first and second pads and between the second and third rows of surface mount pads, the first and second differential pair of circuit lines further extending beyond the second and third rows of surface mount pads.

A method of manufacturing a test apparatus, the method comprising:

• providing a host compliance printed circuit board having a first circuit plane including a first row of surface mount pads, a second row of surface mount pads and a third row of surface mount pads disposed on the first circuit plane, the host compliance board further including a differential pair of circuit lines having one end coupled to the first row of surface mount pads and another end coupled to a fourth row of surface mount pads;
• the second differential circuit line having one end coupled to the second pad, the first and second differential pair of circuit lines extending from the first and second pads and between the second and third rows of surface mount pads, the first and second differential pair of circuit lines further extending beyond the second and third rows of surface mount pads;
• mounting a compression connector to the fourth row of surface mount pads;
• and
• inserting the host compliance printed circuit board into a quad small form factor pluggable double density (QSFP DD) connector, the QSFP DD connector being mounted to a test printed circuit board.