Clock data recovery with decision feedback equalization
AssigneeKandou Labs, S.A.
InventorsAli Hormati, Richard Simpson
Life of this patent
Estimating the term…
Abstract
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
Claims20
A method comprising:
- generating two comparator outputs by sampling a data signal at a sampling instant according to a sampling clock and a historical data decision, the two comparator outputs comprising (i) a data decision of the data signal generated using a first decision feedback equalization (DFE) decision threshold and (ii) an edge trajectory sample of the data signal generated using a second DFE decision threshold;
- generating a phase-error signal based on the edge trajectory sample and the historical data decision;
- and
- providing the phase-error signal to a clock recovery circuit to adjust the sampling instant of the sampling clock to align the second DFE decision threshold with a trajectory of the data signal at the sampling instant.
An apparatus comprising:
- two comparators collectively configured to generate two comparator outputs by sampling a data signal at a sampling instant according to a sampling clock and a historical data decision, the two comparator outputs comprising (i) a data decision of the data signal generated using a first decision feedback equalization (DFE) decision threshold and (ii) an edge trajectory sample of the data signal generated using a second DFE decision threshold;
- a phase-error selection circuit configured to generate a phase-error signal based on the edge trajectory sample and the historical data decision;
- and
- a clock recovery circuit configured to receive the phase-error signal and to responsively adjust the sampling instant of the sampling clock to align the second DFE decision threshold with a trajectory of the data signal at the sampling instant.
Dependencies are inferred from the claim text.